The present invention relates to a single flux quantum circuit utilizing a single flux quantum as an information carrier.
The single flux quantum circuit is a logic circuit using a single flux quantum (below, abbreviated as an SFQ) as an information carrier. The SFQ can be handled as a voltage pulse with a pulse width of several picoseconds. Accordingly, it is possible to implement a not less than 100-GHz high-speed, high-throughput information processing circuit by an SFQ circuit. Further, since the state memory required of the logic circuit is implemented by storing SFQ due to the superconducting loop, it is possible to fabricate a sequential circuit with ease. Further, since the circuit is fabricated of a superconductor, it is possible to implement very low power consumption while maintaining the high speed performance. Up to now, there have been proposed a Josephson transmission line which is the most basic circuit, a basic circuit such as a data flip-flop, and medium scale circuits typified by an adder, a correlator, and the like.
In general, when information is processed by a sequential circuit, in order for the normal operation of the circuit to be guaranteed, setting of the internal state of the sequential circuit at the initial values, i.e., initialization is required. This is because the initial state of the circuit determines the circuit operation to be subsequently developed itself in the sequential circuit. However, in a prior art SFQ circuit, the initialization function has not been regarded as important, and hence it has not been given a sufficient consideration.
For example, a consideration will be given to a sequential circuit in which data flop-flops are connected in cascade. As schematically shown in the equivalent circuit of FIG. 1, in each of data flip-flops DFF1 and DFF2, the one end of a flux quantum storage inductor 305 is connected to an input terminal 307 via a Josephson junction 301, and grounded via a Josephson junction 302. The other end is connected to an output terminal 309, and connected to a clock pulse input terminal 308 via a Josephson junction 303, and further grounded via a Josephson junction 304. The output terminal 309 of the DFF1, and the input terminal 307 of the DFF2 are connected to each other.
The operation of the sequential circuit in accordance with the data flip-flops in FIG. 1 is as follows. Now, it is assumed that the DFF1 and the DFF2 are both in the initial states, i.e., no SFQ is stored in either of the flux quantum storage inductors 305. Therefore, it is assumed that the circulating currents 3061 and 3062 described later are not present in either of the flux quantum storage inductors 3051 and 3052. If an SFQ pulse is inputted to the input terminal 3071 of the DFF1 as a data input in this state, the Josephson junction 3021 is switched to the voltage state, so that the circulating current 3061 flows to the flux quantum storage inductor 3051. Herein, the loop through which the circulating current flows is the loop of the flux quantum storage inductor 3051, the Josephson junction 3041, a grounded circuit, and the Josephson junction 3021. The flowing of the circulating current 3061 results in the data input to the input terminal 3071 being stored in the DFF1. At this step, the voltage of the output terminal 3091 of the DFF1 does not change. Therefore, the input terminal 3072 connected thereto is not affected at all. Then, when clock pulses are inputted from the respective clock pulse input terminals 3081 and 3082 of the DFF1 and DFF2, in the DFF1, the current of the pulse and the circulating current 3061 previously described are superimposed one on another, so that the Josephson junction 3041 is switched to the voltage state. This operation cancels the circulating current 3061 to output the stored data from the output terminal 3091 as a voltage pulse. On the other hand, in the DFF2, no circulating current 3062 is present. Therefore, the clock pulse inputted from the input terminal 3082 is prevented from entering due to the switching of the Josephson junction 3032 to the voltage state. Further, the voltage pulse outputted from the output terminal 3091 of the DFF1 is added to the input terminal 3072 as a data input. Accordingly, the Josephson junction 3022 is switched to the voltage state, so that the circulating current 3062 flows to the flux quantum storage inductor 3052. Namely, the stored contents in the DFF1 are transferred to the DFF2, and stored therein. For adding another input to the DFF1 as a data input, it is proper that an SFQ pulse is inputted to the input terminal 3071 as a data input after the completion of data transfer by the clock pulse.
Thus, the circulating current 306 of each data flip-flop DFF is canceled by the data transfer due to the clock pulse. This invariably involves the operation of emitting the stored data as a voltage pulse from the output terminal 309. Therefore, it is not possible to cancel the circulating current without emitting the pulse from the output terminal. Further, the emission of the voltage pulse results in the input to the data flip-flop DFF of the subsequent stage in the cascaded data flip-flops DFFs. Therefore, it is not possible to cancel the circulating currents of all the DFFs simultaneously by the data transfer due to the clock pulse for initialization.
Examples of the SFQ circuit given a consideration on the initialization function include the circuit referred to as a L-gate in IEEE., Transactions on Applied Superconductivity vol. 9, pp. 3553-3556, 1999. In FIG. 1 of the same literature, there is shown an example wherein a flip-flop circuit is fabricated of L-gates. Then, there is described a configuration method for implementing all the logic functions including the initialization function. However, the whole configuration of the circuit must be implemented as a combination of the L-gates when the initialization function is implemented by adopting the L-gates. For this reason, in the case where the portion requiring the initialization function is a part of the circuit, or other cases, several-fold elements have been necessary for implementing the same function as compared with a prior-art circuit.
It is an object of the present invention to initialize the internal state of a logic circuit having an SFQ storing function by adding a circulating current canceling circuit to only the portion of the circuit requiring the initializing function without requiring the restructuring of the circuit. Further, it is another object of the present invention to achieve the higher functions of a prior-art circuit, and further to implement a complicated logic circuit with less elements and a high margin by utilizing the characteristics resulting from the configuration of the circulating current canceling circuit.
As apparent from the description of FIG. 1, initializing is canceling of the circulating current flowing through a flux quantum storage inductor. In the present invention, therefore, the flux quantum storage inductor is divided into halves, and a Josephson junction is connected to the opened terminal of one inductor of the flux quantum storage inductor divided in halves. At the same time, a circulating current canceling circuit is inserted between the opened terminal of another inductor of the flux quantum storage inductor and a ground terminal. The circulating current canceling circuit is fabricated as follows. It automatically discriminates whether the circulating current is present or not in the flux quantum storage inductor in accordance with the application of an initializing pulse. Thus, it switches the Josephson junction for the division to the voltage state only when the circulating current is present, thereby to cancel the circulating current. It is so fabricated that the initializing pulse is naturally canceled when the circulating current is not present.
Further, by imparting a function of distributing input pulses, or other functions to a prior-art circuit by utilizing the characteristics resulting from the configuration of the circulating current canceling circuit, higher functions of the prior-art circuit is accomplished, and further, a complicated logic circuit is implemented with less elements, and with a high margin.